流水線操作的英文

發(fā)音:

英文翻譯
造句

pile line operation
pipe line operation
pipeline operation
stream line operation
streamline operation

流水線 flow line; assembly line; pi ...
操作 operate; manipulate; handle
宏流水線操作 macropipelining
多級(jí)流水線操作 multilevel pipelining
現(xiàn)有流水線操作工 decoration - assembly line worker
流水線操作流水線運(yùn)算 pipelineoperation
操作流水線 operation pipeline
二次操作流水線 secondary operate pipeline
流水線 flow line; assembly line; pipeline; stream-lined line◇流水線操作 pile line operation; 流水線控制 pipeline control; 流水線生產(chǎn) [工業(yè)] flow-line production; continuous line production; 流水線系統(tǒng) pipeline system; 流水線裝配法 progressive assembly
單線操作 one-line operation
單總線操作 single bus operation
幻線操作 phantom operation
活線操作 hot-line work; live line operation
離線操作 off line operation
聯(lián)線操作 on-line operation
明線操作 open service architecture
曲線操作 curve operation
繞線操作 winding operation
在線操作 on line operation; on-line operation
標(biāo)量流水線 scalar pipeline
不變流水線 fixed assembly line
超流水線 superpipeline
成型流水線 assembling conveyer system
地址流水線 addre pipe; address pipe
紡絲流水線 thread-line

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例句與用法

Achieving the ability to streamline operations
實(shí)現(xiàn)了流水線操作的功能。
One 1995 microprocessor uses this deeper pipeline to achieve a 300 - megahertz clock rate
一臺(tái)1995年生產(chǎn)的微處理器用這種更先進(jìn)的流水線操作可達(dá)到300兆赫的時(shí)鐘頻率。
The pipelining paradox is that it takes the same amount of time to clean a single dirty sock by either method
流水線操作的矛盾在于用任何一種方法洗一雙襪子所用的時(shí)間相等。
Modem superscalar microprocessors try to perform anywhere from three to six instructions in each stage
現(xiàn)代超標(biāo)量體系結(jié)構(gòu)的微處理器努力在流水線操作的每一步中完成三到六條命令。
We introduced advanced product lines and operation mode of japan , also possess many experience managers and skilled workers
公司引進(jìn)了日本先進(jìn)的服裝生產(chǎn)流水線操作模式，現(xiàn)擁有一批經(jīng)驗(yàn)豐富的高素質(zhì)管理隊(duì)伍、技術(shù)過硬的生產(chǎn)員工。
In fact , assuming that each stage takes the same amount of time , the time saved by pipelining is proportional to the number of stages involved
實(shí)際上，假設(shè)每一工作步驟花費(fèi)的時(shí)間相同，流水線操作所節(jié)約的時(shí)間與有關(guān)工作步驟的數(shù)目成比例。
Pipelining , superscalar organization and caches will continue to play major roles in the advancement of microprocessor technology , and if hopes are realized , parallel processing will join them
在微處理器技術(shù)的發(fā)展中，流水線操作、超標(biāo)量體系結(jié)構(gòu)和高速緩沖內(nèi)存儲(chǔ)器仍將扮演著重要的角色。如果可能，平行處理方法也會(huì)加人。
Combining the principles of pipelining and parallelism of dsp with idct theory , we concentrate on the use of multiply - accumulate unit of mcf5272 by merging the operations of addition and multiplication , and realize two dimension of idct with one dimension of idct efficiently . testing shows the software meets the requirement of real - time decoder
重點(diǎn)結(jié)合mcf5272的流水線操作和并行操作特征和反離散余弦變換算法原理，將的二維反離散余弦變換轉(zhuǎn)換成8點(diǎn)的一維反離散余弦變換，利用乘法累加器合并加法運(yùn)算和乘法運(yùn)算高效快速地實(shí)現(xiàn)了反離散余弦變換算法。
The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu , and dwells on 64 - bit vega cpu characteristic , and details the eda technology and the main flow of asic design , and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation , and details cache architecture and mmu . the master dissertation dwells on virtual address translating into physical address , instruction cache finding address and instruction fetching , too
詳細(xì)的闡述了64位vegacpu的特點(diǎn)，闡述了eda技術(shù)和asic設(shè)計(jì)的主要流程，闡述了vegacpu流水線結(jié)構(gòu)、流水線操作、流水線暫停和異常處理，虛擬指令地址的結(jié)構(gòu)和產(chǎn)生， mmu結(jié)構(gòu)，包括指令tlb結(jié)構(gòu)和虛擬指令地址向物理指令地址的生成流程， cache結(jié)構(gòu)，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結(jié)構(gòu)，以及指令的獲取流程。