In both cases we can derive data dependences from reaching definitions and uses information obtained by data flow analysis . at schedule time true register dependencies are known , so register analysis does not involve any complication . but for memory dependencies we have to deal with the problem of aliasing ( addresses are computed during execution ) 而對于存儲器訪問指令而言,其相關性分析則相對復雜得多,關鍵問題是必須解決存儲器訪問地址的別名問題( aliasingproblem ) ,即必須判斷出對存儲器的兩次訪問是否針對同一個地址單元,然后在此基礎上進行存儲器訪問的數據相關性分析。