冗余位的英文

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英文翻譯
造句

redundance bit
redundancy bit
redundancy function
redundant bit
redundant digit

冗余 redundance; redundancy
位 place; location
冗余位校驗 redundancy check
冗余位移 redundant displacement
冗余位數校驗 redundancy check
冗余 redundance; redundancy◇冗余校驗 redundancy check; redundant check; 冗余碼 redundant code; redundance; redundancy; 冗余數 redundant digit; 冗余位 redundancy bit; redundant bit; 冗余狀態 redundant state
余位能 complementary potential energy
多余位移 redundant displacement
膨脹余位 ullage
膨脹余位表 ullage table
多余位數檢驗 redundant check
膨脹余位測板 ullage board; ullage stick
膨脹余位測尺 ullage foot; ullage gauge; ullage scale
膨脹余位測孔 ullage hole; ullage port
損耗膨脹余位 ullage
液艙膨脹余位 ullage
油艙膨脹余位 ullage
單冗余 single redundancy
冗余dna redundant dna; repetitious dna
冗余包 redundancy packet
冗余的 redundancy; redundant
冗余度 degree of redundancy; redundance; redundancy degree; zero of redundancy
冗余環 redundancy loop; redundant loop
冗余件 redundant member
冗余類 lazy class

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例句與用法

After analyzing the two roi coding methods of jpeg2000 standard , their shortcoming is pointed out , and then a novel roi image coding method with utilizing information hiding technique is proposed . in this scheme , some coded information of the background is embedded into the redundant bits of the roi coefficients . the relative quality of rois and background can be adjusted by changing the quantity of embedded information
感興趣區編碼是jpeg2000標準所提供的一項重要特性，本文對標準中規定的兩種感興趣區編碼方法進行了分析，指出其不足之處，而后創造性地提出利用信息隱藏技術來對其進行補充，將部分背景區的編碼信息隱藏在感興趣區系數的冗余位，通過控制嵌入量可以調節感興趣區和背景區的相對質量。
According to research of redundant signed digit ( rsd ) calibration theory of pipelined adc , a novel out of range detection rsd technique is provided . when input signal is out of the adc ’ s range , the technique can detect this situation and the wrong output word is avoided
然后,在深入分析冗余位算法的基礎上,提出了新型的校正算法,針對傳統算法不能判斷信號超出adc處理范圍的不足,增加了溢出判斷功能,既能有效校正比較器的失調,又防止了信號溢出時的誤碼輸出,保證了系統的性能。
Under 0 . 35um si - cmos process , considering the trade off of accuracy and speed in the adc , 2 . 5 - bit were converted in the first stage of the pipeline . using the improved calibration scheme and full difference structure and bottom - plant sampling technique to reduce the errors of the 10 - bit ( 2 . 5 + 1 . 5 5 + 3 ) , 100msample / s pipeline adc
在0 . 35 m工藝水平下,通過折衷考慮提高系統線性度和降低功耗的要求,將流水線第一級精度取為2 . 5位,采用改進的冗余位算法,并結合全差分結構,下底板采樣等技術對一個( 2 . 5 + 1 . 5 5 + 3 )結構的10位100msample / s流水線adc系統進行校正。