hardware language中文什么意思

發音:

用"hardware language"造句

硬件語言

hardware: 〔集合詞〕 1.五金器具；金屬制品。 2.( ...
language: n. 1.語言；(某民族，某國的)國語；語調，措詞。 2 ...
analog hardware description language: 模擬硬件描述語言
computer hardware definition language: 計算機硬件定義語言
computer hardware description language: 計算機描述語言; 計算機硬件描述語言

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例句與用法

This paper has used the hardware language vhdl ( vhsic hardware description language ) to program some special circuit and prepared some work for the system on chip ( soc )
利用硬件描述語言將調速控制所需的一些電路綜合在fpga芯片上為電機控制器向片內系統( soc )方向發展做了一定的工作。
The aim of this paper is to implement the decoder of turbo codes with fpga . the iterative decoding algorithms and how to implement them with hardware language have been discussed in the paper
本文以turbo碼譯碼器的fpga實現為目標,對turbo碼的迭代譯碼算法及用硬件語言實現其譯碼算法進行了深入研究。
Digital image processing consume a large amount of memory and time commonly . basing on the advantage of fpga , the paper design harware module by hdl ( hardware language ) , i . e . , some function is achieved by les ( logic element ) of the fpga . the real - time of digital image processing is achieved by this . the sample and display of digital image is the important part . so , the paper mainly design the sample and desplay module . the sample card is designed and it ’ s word mode is configured according china ’ s cvbs ( composite video bar signal ) . for acquiring the image and storing it correctly to sram , the paper design the sample - control module . the sample module can work correctly using least time . the reliability and real - time achieve the reference . according the vga principle and scheduling of the ths8134 , the paper design a vga - control module by hdl . firstly , the control signal is synthesized secondly , the horirontal and vertical synchronization signals is synthesized according to the vga interface standard
圖像處理的特點是處理的數據量大,處理非常耗時,為實現數字圖像的實時處理,本文研究了在fpga上用硬件描述語言實現功能模塊的方法,通過功能模塊的硬件化,解決了視頻圖像處理的速度問題。圖像數據的正確采集和顯示輸出是其中的兩個重要的模塊,因此,本文主要完成了圖像數據的采集和顯示輸出的設計。本文設計了采集卡,并要對其工作模式進行了配置和編寫了采集控制模塊,在采集控制模塊的控制下,將數字圖像數據正確無誤的存儲到了sram中。
The vxibus c - size and i , q channels are employed in this module design , and the sampling rate in each channel reaches 500mhz . the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ) . the timing and logic function are fulfilled by fpga . after the disscusion of signal adjusted , the detailed scheme of this module design have been showed . in this design , there is much logic function design , and it is very strict with the hardware language program . so the basic flow of hardware program design and several very important methods of high speed logic function design , which is described by vhdl , are introduced . also , expatiated the inner modules structure of fpga for forepart circuit , the keystone and difficulties of the design . the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system , and it is very important . the timing simulating results of several pivotal modules are depicted . high - speed signal paths are terminated to match the characteristic impedance . the design undergoes integrity analysis and software simulation
在本模塊的設計中,有著大量的邏輯設計,對硬件語言程序的編寫要求比較高,因此,文中介紹了硬件程序設計的基本流程,以及幾種基于vhdl硬件語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構,設計的重點、難點,并給出了重要模塊的時序仿真結果。高速pcb的設計也是目前實現高速數據采集系統的難點和重點,文中詳細的闡明了高速pcb設計中的注意點,以及作者在設計本模塊時的經驗和心得。