An error recoverable structure based on complementary logic and alternating - retry 基于互補邏輯和交替重試的差錯恢復結構
To solve this problem , this paper presents a novel dual modular redundancy structure using complementary logic - alternating - complementary logic cl - acl switching mode . during error - free operation , the cl - acl structure operates by complementary logic mode . after an error is detected , it retries by alternating logic mode 在低電源電壓2 . 2v或更低或在0 . 1 m m vlsi工藝條件下,具有大于10 mev能級的宇宙中子流以高達20中子平方厘米小時到達地球表面時所引起的電路的隨機差錯率將是難以接受的。
If all errors belong to single or multiple temporary 0 1 - error or stuck - at - error produced by one module , then these errors can be corrected effectively . the results obtained from the simulation validate the correctness of the cl - acl structure . analytic results show that the delay of the cl - acl structure is dramatically less than that of a dmr structure using alternating - complementary logic mode 這些粒子所引起的干擾不僅將改變存儲單元的邏輯值,而且將導致邏輯電路產生瞬時輸出脈沖,如果這些脈沖在某個關鍵的時間段里產生,比如在時鐘或數據的變化過程中,那么它們將間接地使其它電路的狀態產生變化。